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Description: 此是进行循环冗余效验的Verilog编码,适合多种标准,如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
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Size: 3800 |
Author: 藏瑞 |
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Description: verilog实例 100 多个-more than 100 examples of Verilog
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Size: 189440 |
Author: 地方 |
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Description: 用于计算CRC的verilog HDL源码-CRC calculation for the Verilog HDL source
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Size: 10240 |
Author: 刘波 |
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Description: CRC校验码,用于对数据流进行crc校验。
主要有CRC_16,CRC_8,CRC_32校验。
所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
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Size: 10240 |
Author: 李鹏 |
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Description: 循环冗余校验,crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
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Size: 31744 |
Author: 李鹏 |
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Description: CRC循环校验码的VERILOG源文件,在MODELSIM下的一个工程。-Cyclic Check Code VERILOG source, the MODELSIM of a project.
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Size: 26624 |
Author: 刘仪 |
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Description: 比较完善的CRC编码VerilogHDL描述-more perfect description of CRC coding VerilogHDL
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Size: 4096 |
Author: nil |
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Description: crc校验功能,用硬件语言实现,vhdl或者verilog实现。逻辑功能。-crc check function, hardware language, verilog or vhdl achieve. Logic function.
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Size: 296960 |
Author: likj |
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Description: 循环冗余校验,crc_16,主要运用在数字通信系统。用verilog HDL编写-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared using verilog HDL
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Size: 1024 |
Author: 宋子奇 |
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Description: crc校验,非常好用,是从Xilinx的IP演化来的-crc脨 拢 脩茅 拢 卢 脟 鲁 拢 潞 脙脫脙 拢 卢 脢脟
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Size: 10240 |
Author: zl |
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Description: PCI express CRC rtl core for Fpga/asic Designer
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Size: 202752 |
Author: 李晓媛 |
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Description: CRC校验串行实现方法,verilog源码,利用反馈线性移位寄存器的方法,实现简单,适用于串行通信协议中的CRC校验.-CRC checksum method of serial realize, verilog source code, the use of linear feedback shift register method, the realization of simple serial communication protocol for the CRC checksum.
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Size: 1024 |
Author: 徐亮 |
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Description: CRC校验并行实现,Verilog源码.8位数据输入,实现速度快,适用与各种类型的器件.-Parallel Implementation of CRC checksum, Verilog source code .8-bit data input, to achieve fast, applicable with all types of devices.
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Size: 78848 |
Author: 徐亮 |
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Description: 循环码编码器verilog实现,里面包含有源程序和仿真图。-Cyclic code encoder Verilog realization, which contains the source code and simulation of Fig.
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Size: 15360 |
Author: 萍果 |
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Description: CRC循环冗余检验 Verilog 编码程序-CRC cyclic redundancy test Verilog coding procedures
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Size: 1024 |
Author: yuanxiaonan |
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Description: 利用verilog实现的一个(2,1,2)卷积码的编码器,很有用的哟!-Verilog realize the use of a (2,1,2) convolutional code encoder, yo useful!
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Size: 1024 |
Author: 刘横 |
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Description: crc_table.c is for reset seed( 0000 )
crc_table_1.c is for reset seed( ffff)
CRC16_D8_m.v is a verilog module of byte paralle crc.
CRC16_D8_m_tb.v is the testbench file of above module. -crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.
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Size: 3072 |
Author: 樊文杰 |
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Description: 该文件为多种CRC校验的不同的verilog实现,开发平台为QUATUS2,可直接运行-The document for a variety of different CRC checksum Verilog realize, development platform for QUATUS2, can be directly run
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Size: 10240 |
Author: 金智远 |
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Description: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 8)
// * data width: 8-Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)
//* data width: 8
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Size: 1024 |
Author: yangyi |
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Description: crc校验的程序,关于crc的校验程序,8位转化为8位的并行算法,使用verilog编写的(crc search .12bit_4bit,8_8bit,and16 bit_8bit,32bit_8bit progranming by verilog languages,is very good. I think is correct)
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Size: 6144 |
Author: penjin5
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